1. Field of the Invention
The present invention relates to a method for manufacturing a flash memory device, and more specifically, to a method for manufacturing a flash memory device wherein a hard mask is patterned and an etch process is then performed in a single etch apparatus, forming a control gate and a floating gate.
2. Discussion of Related Art
A conventional method for manufacturing a flash memory device will now be described with reference to the layout of FIG. 1. FIG. 2A to FIG. 6A show cross-sectional views taken along lines A-A′ in FIG. 1, and FIG. 2B to FIG. 6B show cross-sectional views taken along lines B-B′ in FIG. 1.
FIG. 1 is a layout diagram illustrating a NAND type data flash memory device. The NAND type data flash memory device includes an isolation layer 20 for isolating a semiconductor substrate 10 into an active region and a field region at predetermined regions on a semiconductor substrate 10, a floating gate FG a portion of which is overlapped with the isolation layer 20, wherein the floating gate FG is formed on the active region, and a control gate CG formed to intersect the floating gate FG.
FIGS. 2A to 6A and FIG. 2B to FIG. 6B are cross-sectional views for explaining problems of a method for manufacturing a flash memory device in the related art. FIG. 2A to FIG. 6A are cross-sectional views taken along lines A-A′ in FIG. 1, and FIGS. 2B to 6B are cross-sectional views taken along lines B-B′ in FIG. 1.
Referring to FIG. 2A and FIG. 2B, a tunnel oxide layer 103 and a first conductive layer 104 are formed on a semiconductor substrate 101. A self-aligned shallow trench isolation (hereinafter, referred to as “SASTI”) process is then implemented to form an isolation layer 102. A second conductive layer 105 is formed on the entire structure. The second conductive layer 105 is patterned to form a floating gate pattern having first and second conductive layers 104 and 105.
A dielectric layer 106, a third conductive layer 107 and a fourth conductive layer 108 of an ONO structure are formed on the entire structure. After a hard mask layer 109 is formed on the fourth conductive layer 108, a pattering process using a mask for forming a gate electrode is performed to pattern the hard mask layer 109.
Referring to FIG. 3A and FIG. 3B, the fourth conductive layer 108 and the third conductive layer 107 are etched by means of an etch process using the hard mask layer 109. Although the third conductive layer 107 in the active region is stripped, the third conductive layer 107 formed in the field region remains as much as the step of the second conductive layer 105.
By reference to FIG. 4A and FIG. 4B, in order to strip the third conductive layer 107 remaining on the field region, an excessive etch process is performed. At this time, the third conductive layer 107 exposed in the active region is etched by mans of over-etch, resulting in an under cut (L). In other words, there are problems that electrical properties of the device are degraded since the patterned sidewall of the third conductive layer 107 in the active region is recessed during the over-etch.
Referring to FIG. 5, an etch process for stripping the dielectric layer 106 of the ONO structure is performed. At this time, if the second conductive layer 105 is formed in thickness of over 2000 Å in order to secure the coupling ratio, some of the hard mask layer 108 and the isolation layer 102 are damaged in the over-etch process for completely stripping the dielectric layer 106.
Referring to FIG. 6, the second conductive layer 105 is etched. In this process, the first conductive layer 104 beneath the second conductive layer 105 is also etched, thereby isolating a floating gate 110. Thus a gate electrode in which the tunnel oxide layer 103, the isolated floating gate 110, the dielectric layer 106, and the control gates 107 and 108 are stacked is formed.
As described above, the conventional method for manufacturing the flash memory device has problems that mass production margin is very low due to an increased process since the formation process of the control gate and the isolation process of the floating gate are performed in two-fold processes and management of the process and equipment is difficult due to the two-fold etch process.
Furthermore, in an existing flash memory device of below 256M, a second conductive layer is formed in thickness of about 500 Å-1000 Å. Thus a dielectric layer fence can be implemented separately from the floating gate etch process. As electrical reliability depending on mass storage and higher-integration of the flash memory device is increased, the second conductive layer is formed in thickness of over 1500 Å so as to secure a high coupling ratio. As the process of stripping the dielectric layer in the two-fold etch has to be separately performed, a more process time is required.
Meanwhile, another problem in the gate formation process of the conventional NAND type flash memory device is control of critical dimension (CD) and a gate profile in the gate line, and defective management through a plurality of equipments for performing a plurality of processes.
A problem in the final critical dimension of the gate results in variation in the threshold voltage and a sheet resistance problem depending on variation in the coupling ratio and the final critical dimension of the flash memory device. The greater the number of the process for forming the gate line, the greater the number of parameters that affect variation in the critical dimension of the gate line. Resultantly, control of the gate line critical dimension becomes inevitably problematic.
In addition, the control problem of the gate profile is likely to result in inclination of the gate profile or damage of the side profile depending on implementation of three-times dry etches. In a state where the side of the second and third conductive layers exposed when the control gate is experienced by dry etch is exposed, the dielectric layer is experienced by dry etch and an underlying conductive layer is experienced by dry etch. It is thus difficult to control the gate profile.
Furthermore, in securing mass production margin of the flash memory device and improving the yield of the device, reduction in the yield due to defects is an important problem that should be handled in all the memory and non-memory products. This can be basically improved by managing the process and equipment or improving the etch condition. It is, however, preferred that the number of the process is simplified, so that the effect of exposure is reduced. This is the most important problem in the process setup.